Sunil P Khatri's Books

Source-Synchronous Networks-On-Chip

Circuit and Architectural Interconnect Modeling

By: Ayan Mandal,Sunil P. Khatri,Rabi Mahapatra

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Source-Synchronous Networks-On-Chip

Circuit and Architectural Interconnect Modeling

By: Ayan Mandal,Sunil P. Khatri,Rabi Mahapatra

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

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151

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Springer Science & Business Media

Published Date

ISBN 10

1461494052

ISBN 13

9781461494058

Hardware Acceleration of EDA Algorithms

Custom ICs, FPGAs and GPUs

By: Sunil P Khatri,Kanupriya Gulati

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Hardware Acceleration of EDA Algorithms

Custom ICs, FPGAs and GPUs

By: Sunil P Khatri,Kanupriya Gulati

Single-threaded software applications have ceased to see signi?cant gains in p- formance on a general-purpose CPU, even with further scaling in very large scale integration (VLSI) technology. This is a signi?cant problem for electronic design automation (EDA) applications, since the design complexity of VLSI integrated circuits (ICs) is continuously growing. In this research monograph, we evaluate custom ICs, ?eld-programmable gate arrays (FPGAs), and graphics processors as platforms for accelerating EDA algorithms, instead of the general-purpose sing- threaded CPU. We study applications which are used in key time-consuming steps of the VLSI design ?ow. Further, these applications also have different degrees of inherent parallelism in them. We study both control-dominated EDA applications and control plus data parallel EDA applications. We accelerate these applications on these different hardware platforms. We also present an automated approach for accelerating certain uniprocessor applications on a graphics processor. This monograph compares custom ICs, FPGAs, and graphics processing units (GPUs) as potential platforms to accelerate EDA algorithms. It also provides details of the programming model used for interfacing with the GPUs.

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Page Count

207

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Springer Science & Business Media

Published Date

ISBN 10

1441909443

ISBN 13

9781441909442

Logic Synthesis for Genetic Diseases

Modeling Disease Behavior Using Boolean Networks

By: Pey-Chang Kent Lin,Sunil P. Khatri

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Logic Synthesis for Genetic Diseases

Modeling Disease Behavior Using Boolean Networks

By: Pey-Chang Kent Lin,Sunil P. Khatri

This book brings to bear a body of logic synthesis techniques, in order to contribute to the analysis and control of Boolean Networks (BN) for modeling genetic diseases such as cancer. The authors provide several VLSI logic techniques to model the genetic disease behavior as a BN, with powerful implicit enumeration techniques. Coverage also includes techniques from VLSI testing to control a faulty BN, transforming its behavior to a healthy BN, potentially aiding in efforts to find the best candidates for treatment of genetic diseases.

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112

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Springer Science & Business Media

Published Date

ISBN 10

146149429X

ISBN 13

9781461494294

Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

By: Sunil P. Khatri,Robert K. Brayton,Alberto Sangiovanni-Vincentelli

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Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

By: Sunil P. Khatri,Robert K. Brayton,Alberto Sangiovanni-Vincentelli

Three researchers, Khatri (U. of Colorado), Robert Brayton, and Alberto Sangiovanni- Vincentelli (both at the U. of California, Berkeley), propose a new VLSI design based on layout methodologies that eliminates the possibility of cross-talk noise. Following an introduction to VLSI layout fabrics, the authors introduce the standard-cell based design methodology and contrast it with a method that uses a network of Programmable Logic Arrays for the logic circuit. The techniques for performing wire removal in such a network are then described. Annotation copyrighted by Book News Inc., Portland, OR.

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112

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Springer Science & Business Media

Published Date

ISBN 10

079237407X

ISBN 13

9780792374077

On and Off-Chip Crosstalk Avoidance in VLSI Design

By: Chunjie Duan,Brock J. LaMeres

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On and Off-Chip Crosstalk Avoidance in VLSI Design

By: Chunjie Duan,Brock J. LaMeres

Deep Sub-Micron (DSM) processes present many changes to Very Large Scale Integration (VLSI) circuit designers. One of the greatest challenges is crosstalk, which becomes significant with shrinking feature sizes of VLSI fabrication processes. The presence of crosstalk greatly limits the speed and increases the power consumption of the IC design. This book focuses on crosstalk avoidance with bus encoding, one of the techniques that selectively mitigates the impact of crosstalk and improves the speed and power consumption of the bus interconnect. This technique encodes data before transmission over the bus to avoid certain undesirable crosstalk conditions and thereby improve the bus speed and/or energy consumption.

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250

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Springer Science & Business Media

Published Date

ISBN 10

1441909478

ISBN 13

9781441909473

Advanced Techniques in Logic Synthesis, Optimizations and Applications

By: Kanupriya Gulati

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Advanced Techniques in Logic Synthesis, Optimizations and Applications

By: Kanupriya Gulati

This book covers recent advances in the field of logic synthesis and design, including Boolean Matching, Logic Decomposition, Boolean satisfiability, Advanced Synthesis Techniques and Applications of Logic Design. All of these topics are valuable to CAD engineers working in Logic Design, Logic Optimization, and Verification. Engineers seeking opportunities for optimizing VLSI integrated circuits will find this book as an invaluable reference, since there is no existing book that covers this material in a systematic fashion.

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Page Count

423

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Springer Science & Business Media

Published Date

ISBN 10

1441975187

ISBN 13

9781441975188

Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

By: Robert K. Brayton,Alberto L. Sangiovanni-Vincentelli

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Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

By: Robert K. Brayton,Alberto L. Sangiovanni-Vincentelli

This book was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a host of electrical problems like cross-talk, electromigration, self-heat, etc. are becoming important. Cross-talk is one of the major problems since it results in unpredictable design behavior. In particular, it can result in significant delay variation or signal integrity problems in a wire, depending on the state of its neighboring wires. Typical approaches to tackle the cross-talk problem attempt to fix the problem once it is created. In our approach, we ensure that cross-talk is eliminated by design. The work described in this book attempts to take an "outside-the-box" view and propose a radically different design style. This design style first imposes a fixed layout pattern (or fabric) on the integrated circuit, and then embeds the circuit being implemented into this fabric. The fabric is chosen carefully in order to eliminate the cross-talk problem being faced in modem IC processes. With our choice of fabric, cross-talk between adjacent wires on an IC is reduced by between one and two orders of magnitude. In this way, the fabric concept eliminates cross-talk up-front, and by design. We propose two separate design flows, each of which uses the fabric concept to implement logic. The first flow uses fabric-compliant standard cells as an im plementation vehicle. We call these cells fabric cells, and they have the same logic functionality as existing standard cells with which they are compared.

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123

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Springer Science & Business Media

Published Date

ISBN 10

1461514770

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9781461514770

Advanced Techniques in Logic Synthesis, Optimizations and Applications

By: Kanupriya Gulati

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Advanced Techniques in Logic Synthesis, Optimizations and Applications

By: Kanupriya Gulati

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423

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ISBN 10

1441975179

ISBN 13

9781441975171

Hardware Acceleration of EDA Algorithms

Custom ICs, FPGAs and GPUs

By: Sunil P Khatri,Kanupriya Gulati

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Hardware Acceleration of EDA Algorithms

Custom ICs, FPGAs and GPUs

By: Sunil P Khatri,Kanupriya Gulati

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Page Count

207

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Springer Science & Business Media

Published Date

ISBN 10

1441909443

ISBN 13

9781441909442

Analysis and Design of Resilient VLSI Circuits

Mitigating Soft Errors and Process Variations

By: Rajesh Garg

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Analysis and Design of Resilient VLSI Circuits

Mitigating Soft Errors and Process Variations

By: Rajesh Garg

This monograph is motivated by the challenges faced in designing reliable VLSI systems in modern VLSI processes. The reliable operation of integrated circuits (ICs) has become increasingly dif?cult to achieve in the deep submicron (DSM) era. With continuouslydecreasing device feature sizes, combinedwith lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations, and radiation-inducedsoft errors. Among these noise sources, soft errors(or error caused by radiation particle strikes) have become an increasingly troublesome issue for memory arrays as well as c- binational logic circuits. Also, in the DSM era, process variations are increasing at a signi?cant rate, making it more dif?cult to design reliable VLSI circuits. Hence, it is important to ef?ciently design robust VLSI circuits that are resilient to radiation particle strikes and process variations. The work presented in this research mo- graph presents several analysis and design techniques with the goal of realizing VLSI circuits, which are radiation and process variation tolerant.

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224

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Springer Science & Business Media

Published Date

ISBN 10

1441909311

ISBN 13

9781441909312

Logic Synthesis for Genetic Diseases

Modeling Disease Behavior Using Boolean Networks

By: Pey-Chang Kent Lin,Sunil P. Khatri

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Logic Synthesis for Genetic Diseases

Modeling Disease Behavior Using Boolean Networks

By: Pey-Chang Kent Lin,Sunil P. Khatri

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Solve jigsaw puzzle

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Page Count

112

Publisher

Springer Science & Business Media

Published Date

ISBN 10

146149429X

ISBN 13

9781461494294

Source-Synchronous Networks-On-Chip

Circuit and Architectural Interconnect Modeling

By: Ayan Mandal,Sunil P. Khatri,Rabi Mahapatra

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Source-Synchronous Networks-On-Chip

Circuit and Architectural Interconnect Modeling

By: Ayan Mandal,Sunil P. Khatri,Rabi Mahapatra

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Solve jigsaw puzzle

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Page Count

151

Publisher

Springer Science & Business Media

Published Date

ISBN 10

1461494052

ISBN 13

9781461494058

Book's by Sunil P Khatri

Source-Synchronous Networks-On-Chip

Source-Synchronous Networks-On-Chip

Hardware Acceleration of EDA Algorithms

Hardware Acceleration of EDA Algorithms

Logic Synthesis for Genetic Diseases

Logic Synthesis for Genetic Diseases

Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

On and Off-Chip Crosstalk Avoidance in VLSI Design

On and Off-Chip Crosstalk Avoidance in VLSI Design

Advanced Techniques in Logic Synthesis, Optimizations and Applications

Advanced Techniques in Logic Synthesis, Optimizations and Applications

Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

Advanced Techniques in Logic Synthesis, Optimizations and Applications

Advanced Techniques in Logic Synthesis, Optimizations and Applications

Hardware Acceleration of EDA Algorithms

Hardware Acceleration of EDA Algorithms

Analysis and Design of Resilient VLSI Circuits

Analysis and Design of Resilient VLSI Circuits

Logic Synthesis for Genetic Diseases

Logic Synthesis for Genetic Diseases

Source-Synchronous Networks-On-Chip

Source-Synchronous Networks-On-Chip

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