Srinivas Devadas's Books

Sequential Logic Testing and Verification

By: Abhijit Ghosh,Srinivas Devadas,A. Richard Newton

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Sequential Logic Testing and Verification

By: Abhijit Ghosh,Srinivas Devadas,A. Richard Newton

In order to design and build computers that achieve and sustain high performance, it is essential that reliability issues be considered care fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the incidence of failure. For instance, in order design reliable inte gritted circuits, it is necessary to analyze how decisions regarding design rules affect the yield, i.e., the percentage of functional chips obtained by the manufacturing process. Of equal importance in producing reliable computers is the detection of failures in its Very Large Scale Integrated (VLSI) circuit components, caused by errors in the design specification, implementation, or manufacturing processes. Design verification involves the checking of the specification of a design for correctness prior to carrying out an implementation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that there are no manufacturing defects in the integrated circuit. It should be noted that all the above verification mechanisms deal not only with verifying the functionality of the integrated circuit but also its performance.

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224

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Springer Science & Business Media

Published Date

ISBN 10

1461536464

ISBN 13

9781461536468

Computer-Aided Design Techniques for Low Power Sequential Logic Circuits

By: José Monteiro,Srinivas Devadas

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Computer-Aided Design Techniques for Low Power Sequential Logic Circuits

By: José Monteiro,Srinivas Devadas

Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital system determines its heat dissipation as well as battery life. For some systems, power has become the most critical design constraint. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits presents a methodology for low power design. The authors first present a survey of techniques for estimating the average power dissipation of a logic circuit. At the logic level, power dissipation is directly related to average switching activity. A symbolic simulation method that accurately computes the average switching activity in logic circuits is then described. This method is extended to handle sequential logic circuits by modeling correlation in time and by calculating the probabilities of present state lines. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits then presents a survey of methods to optimize logic circuits for low power dissipation which target reduced switching activity. A method to retime a sequential logic circuit where registers are repositioned such that the overall glitching in the circuit is minimized is also described. The authors then detail a powerful optimization method that is based on selectively precomputing the output logic values of a circuit one clock cycle before they are required, and using the precomputed value to reduce internal switching activity in the succeeding clock cycle. Presented next is a survey of methods that reduce switching activity in circuits described at the register-transfer and behavioral levels. Also described is a scheduling algorithm that reduces power dissipation by maximising the inactivity period of the modules in a given circuit. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits concludes with a summary and directions for future research.

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194

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Springer Science & Business Media

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ISBN 10

1461563194

ISBN 13

9781461563198

Computer-Aided Design Techniques for Low Power Sequential Logic Circuits

By: José Monteiro,Srinivas Devadas

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Computer-Aided Design Techniques for Low Power Sequential Logic Circuits

By: José Monteiro,Srinivas Devadas

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194

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Springer Science & Business Media

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1461563194

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9781461563198

Secure Processors Part II

Intel SGX Security Analysis and MIT Sanctum Architecture

By: Victor Costan,Ilia Lebedev,Srinivas Devadas

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Secure Processors Part II

Intel SGX Security Analysis and MIT Sanctum Architecture

By: Victor Costan,Ilia Lebedev,Srinivas Devadas

This manuscript is the second in a two part survey and analysis of the state of the art in secure processor systems, with a specific focus on remote software attestation and software isolation. The first part established the taxonomy and prerequisite concepts relevant to an examination of the state of the art in trusted remote computation: attested software isolation containers (enclaves). This second part extends Part I's description of Intel's Software Guard Extensions (SGX), an available and documented enclave-capable system, with a rigorous security analysis of SGX as a system for trusted remote computation. This part documents the authors' concerns over the shortcomings of SGX as a secure system and introduces the MIT Sanctum processor developed by the authors: a system designed to offer stronger security guarantees, lend itself better to analysis and formal verification, and offer a more straightforward and complete threat model than the Intel system, all with an equivalent programming model. This two part work advocates a principled, transparent, and well-scrutinized approach to system design, and argues that practical guarantees of privacy and integrity for remote computation are achievable at a reasonable design cost and performance overhead.

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112

Published Date

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1680833030

ISBN 13

9781680833034

Book's by Srinivas Devadas

Sequential Logic Testing and Verification

Sequential Logic Testing and Verification

Computer-Aided Design Techniques for Low Power Sequential Logic Circuits

Computer-Aided Design Techniques for Low Power Sequential Logic Circuits

Computer-Aided Design Techniques for Low Power Sequential Logic Circuits

Computer-Aided Design Techniques for Low Power Sequential Logic Circuits

Secure Processors Part II

Secure Processors Part II

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