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Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

By: Pascal Meinerzhagen,Adam Teman,Robert Giterman,Noa Edri,Andreas Burg,Alexander Fish

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Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

By: Pascal Meinerzhagen,Adam Teman,Robert Giterman,Noa Edri,Andreas Burg,Alexander Fish

This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.

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Page Count

151

Publisher

Springer

Published Date

ISBN 10

3319604023

ISBN 13

9783319604022

Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

By: Pascal Meinerzhagen,Adam Teman,Robert Giterman,Noa Edri,Andreas Burg,Alexander Fish

Write a review Read reviews Take a Quiz Solve Book Puzzle

Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip

By: Pascal Meinerzhagen,Adam Teman,Robert Giterman,Noa Edri,Andreas Burg,Alexander Fish

This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.

Average ratings

N/A

5

0%

4

0%

3

0%

2

0%

1

0%

Solve jigsaw puzzle

Age

Page Count

151

Publisher

Springer

Published Date

ISBN 10

3319604023

ISBN 13

9783319604022