Title

Login

Join

Book's by Minsik Cho

Covers

List

Manufacturability Aware Routing in Nanometer VLSI

By: David Z. Pan,Minsik Cho,Kun Yuan

Write a review Read reviews Take a Quiz Solve Book Puzzle

Manufacturability Aware Routing in Nanometer VLSI

By: David Z. Pan,Minsik Cho,Kun Yuan

This paper surveys key research challenges and recent results of manufacturability aware routing in nanometer VLSI designs. The manufacturing challenges have their root causes from various integrated circuit (IC) manufacturing processes and steps, e.g., deep sub-wavelength lithography, random defects, via voids, chemical-mechanical polishing, and antenna-effects. They may result in both functional and parametric yield losses. The manufacturability aware routing can be performed at different routing stages including global routing, track routing, and detail routing, guided by both manufacturing process models and manufacturing-friendly rules. The manufacturability/yield optimization can be performed through both correct-by-construction (i.e., optimization during routing) as well as construct-by-correction (i.e., post-routing optimization). This paper will provide a holistic view of key design for manufacturability issues in nanometer VLSI routing.

Average ratings

N/A

5

0%

4

0%

3

0%

2

0%

1

0%

Solve jigsaw puzzle

Age

Page Count

110

Publisher

Now Publishers Inc

Published Date

ISBN 10

1601983506

ISBN 13

9781601983503

Manufacturability Aware Routing in Nanometer VLSI

By: David Z. Pan,Minsik Cho,Kun Yuan

Write a review Read reviews Take a Quiz Solve Book Puzzle

Manufacturability Aware Routing in Nanometer VLSI

By: David Z. Pan,Minsik Cho,Kun Yuan

This paper surveys key research challenges and recent results of manufacturability aware routing in nanometer VLSI designs. The manufacturing challenges have their root causes from various integrated circuit (IC) manufacturing processes and steps, e.g., deep sub-wavelength lithography, random defects, via voids, chemical-mechanical polishing, and antenna-effects. They may result in both functional and parametric yield losses. The manufacturability aware routing can be performed at different routing stages including global routing, track routing, and detail routing, guided by both manufacturing process models and manufacturing-friendly rules. The manufacturability/yield optimization can be performed through both correct-by-construction (i.e., optimization during routing) as well as construct-by-correction (i.e., post-routing optimization). This paper will provide a holistic view of key design for manufacturability issues in nanometer VLSI routing.

Average ratings

N/A

5

0%

4

0%

3

0%

2

0%

1

0%

Solve jigsaw puzzle

Age

Page Count

110

Publisher

Now Publishers Inc

Published Date

ISBN 10

1601983506

ISBN 13

9781601983503