Margaret Martonosi's Books

Computer Architecture Techniques for Power-Efficiency

By: Stefanos Kaxiras,Margaret Martonosi

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Computer Architecture Techniques for Power-Efficiency

By: Stefanos Kaxiras,Margaret Martonosi

In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. Table of Contents: Introduction / Modeling, Simulation, and Measurement / Using Voltage and Frequency Adjustments to Manage Dynamic Power / Optimizing Capacitance and Switching Activity to Reduce Dynamic Power / Managing Static (Leakage) Power / Conclusions

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207

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Springer Nature

Published Date

ISBN 10

3031017218

ISBN 13

9783031017216

Power-Efficient Computer Architectures

Recent Advances

By: Magnus Själander,Margaret Martonosi,Stefanos Kaxiras

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Power-Efficient Computer Architectures

Recent Advances

By: Magnus Själander,Margaret Martonosi,Stefanos Kaxiras

As Moore's Law and Dennard scaling trends have slowed, the challenges of building high-performance computer architectures while maintaining acceptable power efficiency levels have heightened. Over the past ten years, architecture techniques for power efficiency have shifted from primarily focusing on module-level efficiencies, toward more holistic design styles based on parallelism and heterogeneity. This work highlights and synthesizes recent techniques and trends in power-efficient computer architecture. Table of Contents: Introduction / Voltage and Frequency Management / Heterogeneity and Specialization / Communication and Memory Systems / Conclusions / Bibliography / Authors' Biographies

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Springer Nature

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ISBN 10

3031017455

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9783031017452

General-Purpose Graphics Processor Architecture

By: Tor M. Aamodt,Wilson Wai Lun Fung,Timothy G. Rogers

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General-Purpose Graphics Processor Architecture

By: Tor M. Aamodt,Wilson Wai Lun Fung,Timothy G. Rogers

Originally developed to support video games, graphics processor units (GPUs) are now increasingly used for general-purpose (non-graphics) applications ranging from machine learning to mining of cryptographic currencies. GPUs can achieve improved performance and efficiency versus central processing units (CPUs) by dedicating a larger fraction of hardware resources to computation. In addition, their general-purpose programmability makes contemporary GPUs appealing to software developers in comparison to domain-specific accelerators. This book provides an introduction to those interested in studying the architecture of GPUs that support general-purpose computing. It collects together information currently only found among a wide range of disparate sources. The authors led development of the GPGPU-Sim simulator widely used in academic research on GPU architectures. The first chapter of this book describes the basic hardware structure of GPUs and provides a brief overview of their history. Chapter 2 provides a summary of GPU programming models relevant to the rest of the book. Chapter 3 explores the architecture of GPU compute cores. Chapter 4 explores the architecture of the GPU memory system. After describing the architecture of existing systems, Chapters \ref{ch03} and \ref{ch04} provide an overview of related research. Chapter 5 summarizes cross-cutting research impacting both the compute core and memory system. This book should provide a valuable resource for those wishing to understand the architecture of graphics processor units (GPUs) used for acceleration of general-purpose applications and to those who want to obtain an introduction to the rapidly growing body of research exploring how to improve the architecture of these GPUs.

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140

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Synthesis Lectures on Computer

Published Date

ISBN 10

1627059237

ISBN 13

9781627059237

Innovations in the Memory System

By: Rajeev Balasubramonian

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Innovations in the Memory System

By: Rajeev Balasubramonian

This is a tour through recent and prominent works regarding new DRAM chip designs and technologies, near data processing approaches, new memory channel architectures, techniques to tolerate the overheads of refresh and fault tolerance, security attacks and mitigations, and memory scheduling. The memory system will soon be a hub for future innovation. While conventional memory systems focused primarily on high density, other memory system metrics like energy, security, and reliability are grabbing modern research headlines. With processor performance stagnating, it is also time to consider new programming models that move some application computations into the memory system. This, in turn, will lead to feature-rich memory systems with new interfaces. The past decade has seen a number of memory system innovations that point to this future where the memory system will be much more than dense rows of unintelligent bits.

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151

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Synthesis Lectures on Computer

Published Date

ISBN 10

1627056424

ISBN 13

9781627056427

On-chip Networks

By: Natalie Enright Jerger,Margaret Martonosi,Tushar Krishna,Li-Shiuan Peh

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On-chip Networks

By: Natalie Enright Jerger,Margaret Martonosi,Tushar Krishna,Li-Shiuan Peh

This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. It is a resource for both understanding on-chip network basics and for providing an overview of state of the-art research in on-chip networks. We believe that an overview that teaches both fundamental concepts and highlights state-of-the-art designs will be of great value to both graduate students and industry engineers. While not an exhaustive text, we hope to illuminate fundamental concepts for the reader as well as identify trends and gaps in on-chip network research. With the rapid advances in this field, we felt it was timely to update and review the state of the art in this second edition. We introduce two new chapters at the end of the book. We have updated the latest research of the past years throughout the book and also expanded our coverage of fundamental concepts to include several research ideas that have now made their way into products and, in our opinion, should be textbook concepts that all on-chip network practitioners should know. For example, these fundamental concepts include message passing, multicast routing, and bubble flow control schemes.

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210

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Synthesis Lectures on Computer

Published Date

ISBN 10

1681736721

ISBN 13

9781681736723

A Primer on Memory Consistency and Cache Coherence: Second Edition

By: Vijay Nagarajan,Daniel J. Sorin,Mark D. Hill,David a Wood

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A Primer on Memory Consistency and Cache Coherence: Second Edition

By: Vijay Nagarajan,Daniel J. Sorin,Mark D. Hill,David a Wood

Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems. This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.

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294

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Synthesis Lectures on Computer

Published Date

ISBN 10

1681737116

ISBN 13

9781681737119

Deep Learning for Computer Architects

By: Brandon Reagen,Robert Adolf,Paul Whatmough

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Deep Learning for Computer Architects

By: Brandon Reagen,Robert Adolf,Paul Whatmough

Machine learning, and specifically deep learning, has been hugely disruptive in many fields of computer science. The success of deep learning techniques in solving notoriously difficult classification and regression problems has resulted in their rapid adoption in solving real-world problems. The emergence of deep learning is widely attributed to a virtuous cycle whereby fundamental advancements in training deeper models were enabled by the availability of massive datasets and high-performance computer hardware. This text serves as a primer for computer architects in a new and rapidly evolving field. We review how machine learning has evolved since its inception in the 1960s and track the key developments leading up to the emergence of the powerful deep learning techniques that emerged in the last decade. Next we review representative workloads, including the most commonly used datasets and seminal networks across a variety of domains. In addition to discussing the workloads themselves, we also detail the most popular deep learning tools and show how aspiring practitioners can use the tools with the workloads to characterize and optimize DNNs. The remainder of the book is dedicated to the design and optimization of hardware and architectures for machine learning. As high-performance hardware was so instrumental in the success of machine learning becoming a practical solution, this chapter recounts a variety of optimizations proposed recently to further improve future designs. Finally, we present a review of recent research published in the area as well as a taxonomy to help readers understand how various contributions fall in context.

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123

Published Date

ISBN 10

168173219X

ISBN 13

9781681732190

The Datacenter as a Computer

Designing Warehouse-Scale Machines, Third Edition

By: Luiz André Barroso,Urs Hölzle,Parthasarathy Ranganathan

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The Datacenter as a Computer

Designing Warehouse-Scale Machines, Third Edition

By: Luiz André Barroso,Urs Hölzle,Parthasarathy Ranganathan

This book describes warehouse-scale computers (WSCs), the computing platforms that power cloud computing and all the great web services we use every day. It discusses how these new systems treat the datacenter itself as one massive computer designed at warehouse scale, with hardware and software working in concert to deliver good levels of internet service performance. The book details the architecture of WSCs and covers the main factors influencing their design, operation, and cost structure, and the characteristics of their software base. Each chapter contains multiple real-world examples, including detailed case studies and previously unpublished details of the infrastructure used to power Google's online services. Targeted at the architects and programmers of today's WSCs, this book provides a great foundation for those looking to innovate in this fascinating and important area, but the material will also be broadly interesting to those who just want to understand the infrastructure powering the internet. The third edition reflects four years of advancements since the previous edition and nearly doubles the number of pictures and figures. New topics range from additional workloads like video streaming, machine learning, and public cloud to specialized silicon accelerators, storage and network building blocks, and a revised discussion of data center power and cooling, and uptime. Further discussions of emerging trends and opportunities ensure that this revised edition will remain an essential resource for educators and professionals working on the next generation of WSCs.

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207

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Morgan & Claypool

Published Date

ISBN 10

1681734354

ISBN 13

9781681734354

Principles of Secure Processor Architecture Design

By: Jakub Szefer

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Principles of Secure Processor Architecture Design

By: Jakub Szefer

With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today's processors has increased significantly over the recent years. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today. This book aims to give readers insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered). This book aims to present the different challenges of secure processor architecture design to graduate students interested in research on architecture and hardware security and computer architects working in industry interested in adding security features to their designs. It aims to educate readers about how the different challenges have been solved in the past and what are the best practices, i.e., the principles, for design of new secure processor architectures. Based on the careful review of past work by many computer architects and security researchers, readers also will come to know the five basic principles needed for secure processor architecture design. The book also presents existing research challenges and potential new research directions. Finally, this book presents numerous design suggestions, as well as discusses pitfalls and fallacies that designers should avoid.

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173

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Morgan & Claypool

Published Date

ISBN 10

1681730014

ISBN 13

9781681730011

Compiling Algorithms for Heterogeneous Systems

By: Steven Bell,Jing Pu,James Hegarty,Mark Alan Horowitz

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Compiling Algorithms for Heterogeneous Systems

By: Steven Bell,Jing Pu,James Hegarty,Mark Alan Horowitz

Most emerging applications in imaging and machine learning must perform immense amounts of computation while holding to strict limits on energy and power. To meet these goals, architects are building increasingly specialized compute engines tailored for these specific tasks. The resulting computer systems are heterogeneous, containing multiple processing cores with wildly different execution models. Unfortunately, the cost of producing this specialized hardware--and the software to control it--is astronomical. Moreover, the task of porting algorithms to these heterogeneous machines typically requires that the algorithm be partitioned across the machine and rewritten for each specific architecture, which is time consuming and prone to error. Over the last several years, the authors have approached this problem using domain-specific languages (DSLs): high-level programming languages customized for specific domains, such as database manipulation, machine learning, or image processing. By giving up generality, these languages are able to provide high-level abstractions to the developer while producing high performance output. The purpose of this book is to spur the adoption and the creation of domain-specific languages, especially for the task of creating hardware designs. In the first chapter, a short historical journey explains the forces driving computer architecture today. Chapter 2 describes the various methods for producing designs for accelerators, outlining the push for more abstraction and the tools that enable designers to work at a higher conceptual level. From there, Chapter 3 provides a brief introduction to image processing algorithms and hardware design patterns for implementing them. Chapters 4 and 5 describe and compare Darkroom and Halide, two domain-specific languages created for image processing that produce high-performance designs for both FPGAs and CPUs from the same source code, enabling rapid design cycles and quick porting of algorithms. The final section describes how the DSL approach also simplifies the problem of interfacing between application code and the accelerator by generating the driver stack in addition to the accelerator configuration. This book should serve as a useful introduction to domain-specialized computing for computer architecture students and as a primer on domain-specific languages and image processing hardware for those with more experience in the field.

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105

Publisher

Morgan & Claypool

Published Date

ISBN 10

162705961X

ISBN 13

9781627059619

Hardware and Software Support for Virtualization

By: Edouard Bugnion,Jason Nieh,Dan Tsafrir

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Hardware and Software Support for Virtualization

By: Edouard Bugnion,Jason Nieh,Dan Tsafrir

This book focuses on the core question of the necessary architectural support provided by hardware to efficiently run virtual machines, and of the corresponding design of the hypervisors that run them. Virtualization is still possible when the instruction set architecture lacks such support, but the hypervisor remains more complex and must rely on additional techniques. Despite the focus on architectural support in current architectures, some historical perspective is necessary to appropriately frame the problem. The first half of the book provides the historical perspective of the theoretical framework developed four decades ago by Popek and Goldberg. It also describes earlier systems that enabled virtualization despite the lack of architectural support in hardware. As is often the case, theory defines a necessary--but not sufficient--set of features, and modern architectures are the result of the combination of the theoretical framework with insights derived from practical systems. The second half of the book describes state-of-the-art support for virtualization in both x86-64 and ARM processors. This book includes an in-depth description of the CPU, memory, and I/O virtualization of these two processor architectures, as well as case studies on the Linux/KVM, VMware, and Xen hypervisors. It concludes with a performance comparison of virtualization on current-generation x86- and ARM-based systems across multiple hypervisors.

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206

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ISBN 10

1681732289

ISBN 13

9781681732282

Computer Architecture Techniques for Power-Efficiency

By: Stefanos Kaxiras,Margaret Martonosi

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Computer Architecture Techniques for Power-Efficiency

By: Stefanos Kaxiras,Margaret Martonosi

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219

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Morgan & Claypool Publishers

Published Date

ISBN 10

1598292099

ISBN 13

9781598292091

Power-Efficient Computer Architectures

Recent Advances

By: Magnus Själander,Margaret Martonosi,Stefanos Kaxiras

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Power-Efficient Computer Architectures

Recent Advances

By: Magnus Själander,Margaret Martonosi,Stefanos Kaxiras

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Morgan & Claypool Publishers

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ISBN 10

1627056467

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9781627056465

Space-Time Computing with Temporal Neural Networks

By: James E. Smith

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Space-Time Computing with Temporal Neural Networks

By: James E. Smith

Understanding and implementing the brain's computational paradigm is the one true grand challenge facing computer researchers. Not only are the brain's computational capabilities far beyond those of conventional computers, its energy efficiency is truly remarkable. This book, written from the perspective of a computer designer and targeted at computer researchers, is intended to give both background and lay out a course of action for studying the brain's computational paradigm. It contains a mix of concepts and ideas drawn from computational neuroscience, combined with those of the author. As background, relevant biological features are described in terms of their computational and communication properties. The brain's neocortex is constructed of massively interconnected neurons that compute and communicate via voltage spikes, and a strong argument can be made that precise spike timing is an essential element of the paradigm. Drawing from the biological features, a mathematics-based computational paradigm is constructed. The key feature is spiking neurons that perform communication and processing in space-time, with emphasis on time. In these paradigms, time is used as a freely available resource for both communication and computation. Neuron models are first discussed in general, and one is chosen for detailed development. Using the model, single-neuron computation is first explored. Neuron inputs are encoded as spike patterns, and the neuron is trained to identify input pattern similarities. Individual neurons are building blocks for constructing larger ensembles, referred to as "columns". These columns are trained in an unsupervised manner and operate collectively to perform the basic cognitive function of pattern clustering. Similar input patterns are mapped to a much smaller set of similar output patterns, thereby dividing the input patterns into identifiable clusters. Larger cognitive systems are formed by combining columns into a hierarchical architecture. These higher level architectures are the subject of ongoing study, and progress to date is described in detail in later chapters. Simulation plays a major role in model development, and the simulation infrastructure developed by the author is described.

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215

Publisher

Morgan & Claypool

Published Date

ISBN 10

1627059482

ISBN 13

9781627059480

Memoirs of Margaret Fuller Ossoli

Volume 2

By: Margaret Fuller

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Memoirs of Margaret Fuller Ossoli

Volume 2

By: Margaret Fuller

Reproduction of the original: Memoirs of Margaret Fuller Ossoli by Margaret Fuller

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Page Count

266

Publisher

Outlook Verlag

Published Date

ISBN 10

3752307048

ISBN 13

9783752307047

Memoirs of Margaret Fuller Ossoli

Volume 1

By: Margaret Fuller

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Memoirs of Margaret Fuller Ossoli

Volume 1

By: Margaret Fuller

Reproduction of the original: Memoirs of Margaret Fuller Ossoli by Margaret Fuller

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254

Publisher

Outlook Verlag

Published Date

ISBN 10

375230703X

ISBN 13

9783752307030

Margaret Mead

The Complete Bibliography, 1925-1975

By: Margaret Mead

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Margaret Mead

The Complete Bibliography, 1925-1975

By: Margaret Mead

The book contains a full bibliography, missing only the last few years, and an introduction by Mead on her writings.

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Page Count

216

Publisher

Walter de Gruyter

Published Date

ISBN 10

9027930260

ISBN 13

9789027930262

Memoirs of Margaret Fuller Ossoli

By: Margaret Fuller Ossoli

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Memoirs of Margaret Fuller Ossoli

By: Margaret Fuller Ossoli

This collection of literature attempts to compile many classics that have stood the test of time and offer them at a reduced, affordable price in an attractive volume so that everyone can enjoy them.

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152

Publisher

Createspace Independent Publishing Platform

Published Date

ISBN 10

1519675879

ISBN 13

9781519675873

To Cherish the Life of the World

The Selected Letters of Margaret Mead

By: Margaret Mead

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To Cherish the Life of the World

The Selected Letters of Margaret Mead

By: Margaret Mead

This first collection of Margaret Mead's personal correspondence creates a vivid and intimate portrait of an American icon--with a foreword by Mead's daughter, Mary Catherine Bateson.

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Page Count

474

Published Date

ISBN 10

0465008151

ISBN 13

9780465008155

Book's by Margaret Martonosi

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