The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives. However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to the synchronous RTL-to-GDSII flow) for asynchronous circuits. The purpose of this paper is to counteract this view by presenting design flows that can tackle large designs without significant changes with respect to synchronous design flow. We are limiting ourselves to four design flows that we believe to be closest to this goal. We start from the Tangram flow, because it is the most commercially proven and it is one of the oldest from a methodological point of view. The other three flows (Null Convention Logic, de-synchronization, and gate-level pipelining) could be considered together as asynchronous re-implementations of synchronous (RTL- or gate-level) specifications. The main common idea is substituting the global clocks by local synchronizations. Their most important aspect is to open the possibility to implement large legacy synchronous designs in an almost "push button" manner, where all asynchronous machinery is hidden, so that synchronous RTL designers do not need to be re-educated. These three flows offer a trade-off from very low overhead, almost synchronous implementations, to very high performance, extremely robust dual-rail pipelines.
This book is the result of a long friendship, of a broad international co operation, and of a bold dream. It is the summary of work carried out by the authors, and several other wonderful people, during more than 15 years, across 3 continents, in the course of countless meetings, workshops and discus sions. It shows that neither language nor distance can be an obstacle to close scientific cooperation, when there is unity of goals and true collaboration. When we started, we had very different approaches to handling the mys terious, almost magical world of asynchronous circuits. Some were more theo retical, some were closer to physical reality, some were driven mostly by design needs. In the end, we all shared the same belief that true Electronic Design Automation research must be solidly grounded in formal models, practically minded to avoid excessive complexity, and tested "in the field" in the form of experimental tools. The results are this book, and the CAD tool petrify. The latter can be downloaded and tried by anybody bold (or desperate) enough to tread into the clockless (but not lawless) domain of small-scale asynchronicity. The URL is http://www.lsi. upc. esr j ordic/petrify. We believe that asynchronous circuits are a wonderful object, that aban dons some of the almost militaristic law and order that governs synchronous circuits, to improve in terms of simplicity, energy efficiency and performance.
Embedded systems are informally defined as a collection of programmable parts surrounded by ASICs and other standard components, that interact continuously with an environment through sensors and actuators. The programmable parts include micro-controllers and Digital Signal Processors (DSPs). Embedded systems are often used in life-critical situations, where reliability and safety are more important criteria than performance. Today, embedded systems are designed with an ad hoc approach that is heavily based on earlier experience with similar products and on manual design. Use of higher-level languages such as C helps structure the design somewhat, but with increasing complexity it is not sufficient. Formal verification and automatic synthesis of implementations are the surest ways to guarantee safety. Thus, the POLIS system which is a co-design environment for embedded systems is based on a formal model of computation. POLIS was initiated in 1988 as a research project at the University of California at Berkeley and, over the years, grew into a full design methodology with a software system supporting it. Hardware-Software Co-Design of Embedded Systems: The POLIS Approach is intended to give a complete overview of the POLIS system including its formal and algorithmic aspects. Hardware-Software Co-Design of Embedded Systems: The POLIS Approach will be of interest to embedded system designers (automotive electronics, consumer electronics and telecommunications), micro-controller designers, CAD developers and students.
Since the second half of the 1980s asynchronous circuits have been the subject of a great deal of research following a period of relative oblivion. The lack of interest in asynchronous techniques was motivated by the progressive shift towards synchronous design techniques that had much more structure and were much easier to verify and synthesize. System design requirements made it impossible to eliminate totally the use of asynchronous circuits. Given the objective difficulty encountered by designers, the asynchronous components of electronic systems such as interfaces became a serious bottleneck in the design process. The use of new models and some theoretical breakthroughs made it possible to develop asynchronous design techniques that were reliable and effective. This book describes a variety of mathematical models and of algorithms that form the backbone and the body of a new design methodology for asyn chronous design. The book is intended for asynchronous hardware designers, for computer-aided tool experts, and for digital designers interested in ex ploring the possibility of designing asynchronous circuits. It requires a solid mathematical background in discrete event systems and algorithms. While the book has not been written as a textbook, nevertheless it could be used as a reference book in an advanced course in logic synthesis or asynchronous design.
Relativistic hydrodynamics is a very successful theoretical framework to describe the dynamics of matter from scales as small as those of colliding elementary particles, up to the largest scales in the universe. This book provides an up-to-date, lively, and approachable introduction to the mathematical formalism, numerical techniques, and applications of relativistic hydrodynamics. The topic is typically covered either by very formal or by very phenomenological books, but is instead presented here in a form that will be appreciated both by students and researchers in the field. The topics covered in the book are the results of work carried out over the last 40 years, which can be found in rather technical research articles with dissimilar notations and styles. The book is not just a collection of scattered information, but a well-organized description of relativistic hydrodynamics, from the basic principles of statistical kinetic theory, down to the technical aspects of numerical methods devised for the solution of the equations, and over to the applications in modern physics and astrophysics. Numerous figures, diagrams, and a variety of exercises aid the material in the book. The most obvious applications of this work range from astrophysics (black holes, neutron stars, gamma-ray bursts, and active galaxies) to cosmology (early-universe hydrodynamics and phase transitions) and particle physics (heavy-ion collisions). It is often said that fluids are either seen as solutions of partial differential equations or as "wet". Fluids in this book are definitely wet, but the mathematical beauty of differential equations is not washed out.
This book is the result of a long friendship, of a broad international co operation, and of a bold dream. It is the summary of work carried out by the authors, and several other wonderful people, during more than 15 years, across 3 continents, in the course of countless meetings, workshops and discus sions. It shows that neither language nor distance can be an obstacle to close scientific cooperation, when there is unity of goals and true collaboration. When we started, we had very different approaches to handling the mys terious, almost magical world of asynchronous circuits. Some were more theo retical, some were closer to physical reality, some were driven mostly by design needs. In the end, we all shared the same belief that true Electronic Design Automation research must be solidly grounded in formal models, practically minded to avoid excessive complexity, and tested "in the field" in the form of experimental tools. The results are this book, and the CAD tool petrify. The latter can be downloaded and tried by anybody bold (or desperate) enough to tread into the clockless (but not lawless) domain of small-scale asynchronicity. The URL is http://www.lsi. upc. esr j ordic/petrify. We believe that asynchronous circuits are a wonderful object, that aban dons some of the almost militaristic law and order that governs synchronous circuits, to improve in terms of simplicity, energy efficiency and performance.
The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives. However, the electronics industry for the most part is still reluctant to adopt asynchronous design (with a few notable exceptions) due to a common belief that we still lack a commercial-quality Electronic Design Automation tools (similar to the synchronous RTL-to-GDSII flow) for asynchronous circuits. The purpose of this paper is to counteract this view by presenting design flows that can tackle large designs without significant changes with respect to synchronous design flow. We are limiting ourselves to four design flows that we believe to be closest to this goal. We start from the Tangram flow, because it is the most commercially proven and it is one of the oldest from a methodological point of view. The other three flows (Null Convention Logic, de-synchronization, and gate-level pipelining) could be considered together as asynchronous re-implementations of synchronous (RTL- or gate-level) specifications. The main common idea is substituting the global clocks by local synchronizations. Their most important aspect is to open the possibility to implement large legacy synchronous designs in an almost "push button" manner, where all asynchronous machinery is hidden, so that synchronous RTL designers do not need to be re-educated. These three flows offer a trade-off from very low overhead, almost synchronous implementations, to very high performance, extremely robust dual-rail pipelines.
Since the second half of the 1980s asynchronous circuits have been the subject of a great deal of research following a period of relative oblivion. The lack of interest in asynchronous techniques was motivated by the progressive shift towards synchronous design techniques that had much more structure and were much easier to verify and synthesize. System design requirements made it impossible to eliminate totally the use of asynchronous circuits. Given the objective difficulty encountered by designers, the asynchronous components of electronic systems such as interfaces became a serious bottleneck in the design process. The use of new models and some theoretical breakthroughs made it possible to develop asynchronous design techniques that were reliable and effective. This book describes a variety of mathematical models and of algorithms that form the backbone and the body of a new design methodology for asyn chronous design. The book is intended for asynchronous hardware designers, for computer-aided tool experts, and for digital designers interested in ex ploring the possibility of designing asynchronous circuits. It requires a solid mathematical background in discrete event systems and algorithms. While the book has not been written as a textbook, nevertheless it could be used as a reference book in an advanced course in logic synthesis or asynchronous design.
Embedded systems are informally defined as a collection of programmable parts surrounded by ASICs and other standard components, that interact continuously with an environment through sensors and actuators. The programmable parts include micro-controllers and Digital Signal Processors (DSPs). Embedded systems are often used in life-critical situations, where reliability and safety are more important criteria than performance. Today, embedded systems are designed with an ad hoc approach that is heavily based on earlier experience with similar products and on manual design. Use of higher-level languages such as C helps structure the design somewhat, but with increasing complexity it is not sufficient. Formal verification and automatic synthesis of implementations are the surest ways to guarantee safety. Thus, the POLIS system which is a co-design environment for embedded systems is based on a formal model of computation. POLIS was initiated in 1988 as a research project at the University of California at Berkeley and, over the years, grew into a full design methodology with a software system supporting it. Hardware-Software Co-Design of Embedded Systems: The POLIS Approach is intended to give a complete overview of the POLIS system including its formal and algorithmic aspects. Hardware-Software Co-Design of Embedded Systems: The POLIS Approach will be of interest to embedded system designers (automotive electronics, consumer electronics and telecommunications), micro-controller designers, CAD developers and students.
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