David V. Overhauser's Books

Digital Timing Macromodeling for VLSI Design Verification

By: Jeong-Taek Kong,David V. Overhauser

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Digital Timing Macromodeling for VLSI Design Verification

By: Jeong-Taek Kong,David V. Overhauser

Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.

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Page Count

276

Publisher

Springer Science & Business Media

Published Date

ISBN 10

1461523214

ISBN 13

9781461523215

Switch-Level Timing Simulation of MOS VLSI Circuits

By: Vasant B. Rao,David V. Overhauser,Timothy N. Trick,Ibrahim N. Hajj

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Switch-Level Timing Simulation of MOS VLSI Circuits

By: Vasant B. Rao,David V. Overhauser,Timothy N. Trick,Ibrahim N. Hajj

Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.

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Page Count

218

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Springer Science & Business Media

Published Date

ISBN 10

1461317096

ISBN 13

9781461317098

An Angel Is Calling

By: David Gaddis

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An Angel Is Calling

By: David Gaddis

An Angel is Calling offers a shocking look into the world of big business and the abuses of the American justice system."--Book cover

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Page Count

364

Publisher

Tate Publishing

Published Date

ISBN 10

1616636548

ISBN 13

9781616636548

Book's by David V. Overhauser

Digital Timing Macromodeling for VLSI Design Verification

Digital Timing Macromodeling for VLSI Design Verification

Switch-Level Timing Simulation of MOS VLSI Circuits

Switch-Level Timing Simulation of MOS VLSI Circuits

An Angel Is Calling

An Angel Is Calling

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