David J. Allstot's Books

Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits

By: Nishath K. Verghese,Timothy J. Schmerbeck,David J. Allstot

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Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits

By: Nishath K. Verghese,Timothy J. Schmerbeck,David J. Allstot

The goal of putting `systems on a chip' has been a difficult challenge that is only recently being met. Since the world is `analog', putting systems on a chip requires putting analog interfaces on the same chip as digital processing functions. Since some processing functions are accomplished more efficiently in analog circuitry, chips with a large amount of analog and digital circuitry are being designed. Whether a small amount of analog circuitry is combined with varying amounts of digital circuitry or the other way around, the problem encountered in marrying analog and digital circuitry are the same but with different scope. Some of the most prevalent problems are chip/package capacitive and inductive coupling, ringing on the RLC tuned circuits that form the chip/package power supply rails and off-chip drivers and receivers, coupling between circuits through the chip substrate bulk, and radiated emissions from the chip/package interconnects. To aggravate the problems of designers who have to deal with the complexity of mixed-signal coupling there is a lack of verification techniques to simulate the problem. In addition to considering RLC models for the various chip/package/board level parasitics, mixed-signal circuit designers must also model coupling through the common substrate when simulating ICs to obtain an accurate estimate of coupled noise in their designs. Unfortunately, accurate simulation of substrate coupling has only recently begun to receive attention, and techniques for the same are not widely known. Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits addresses two major issues of the mixed-signal coupling problem -- how to simulate it and how to overcome it. It identifies some of the problems that will be encountered, gives examples of actual hardware experiences, offers simulation techniques, and suggests possible solutions. Readers of this book should come away with a clear directive to simulate their design for interactions prior to building the design, versus a `build it and see' mentality.

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Page Count

297

Publisher

Springer Science & Business Media

Published Date

ISBN 10

1461522390

ISBN 13

9781461522393

Parasitic-Aware Optimization of CMOS RF Circuits

By: David J. Allstot,Jinho Park,Kiyong Choi

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Parasitic-Aware Optimization of CMOS RF Circuits

By: David J. Allstot,Jinho Park,Kiyong Choi

In the arena of parasitic-aware design of CMOS RF circuits, efforts are aimed at the realization of true single-chip radios with few, if any, off-chip components. The parasitic-aware RF circuit synthesis techniques described in this book effectively address critical problems in this field.

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Page Count

169

Publisher

Springer Science & Business Media

Published Date

ISBN 10

0306481294

ISBN 13

9780306481291

Digital Timing Macromodeling for VLSI Design Verification

By: Jeong-Taek Kong,David V. Overhauser

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Digital Timing Macromodeling for VLSI Design Verification

By: Jeong-Taek Kong,David V. Overhauser

Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.

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Page Count

276

Publisher

Springer Science & Business Media

Published Date

ISBN 10

1461523214

ISBN 13

9781461523215

Book's by David J. Allstot

Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits

Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits

Parasitic-Aware Optimization of CMOS RF Circuits

Parasitic-Aware Optimization of CMOS RF Circuits

Digital Timing Macromodeling for VLSI Design Verification

Digital Timing Macromodeling for VLSI Design Verification

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